EDN

SpringSoft turns the power of Verdi on SystemVerilog test benches

SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...
Design-Reuse

Unifying Diversity -- A classic example of Reusability

Gaurav Jalan, SiRF Technology India Pvt. Ltd. Sandeep Ahuja, SiRF Technology India Pvt. Ltd. Globalization is the talk of the industry for quite some time. It brings us to the idea that; we now feel ...
EDN

Using Tcl to create a virtual component in Verilog

It has long been a goal to put realistic prototypes or models into system developer's hands as soon as possible. This has been accomplished with FPGAs, C language models and sometimes co-simulation ...
Semiconductor Engineering

Quality time?

System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional ...
Design-Reuse

Complex SoC Verification using ARM Processor

Technology evolution, in part, has enabled the transition of multi-million gate designs from large printed circuit boards to SoC (System on Chip). The major advantages of SoC include low cost per gate ...
Electronic Design

Development Environment Supports Mixed C++ And HDL Test Benches

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verification capabilities, ...
Business Insider

Compound Photonics Selects Velocity CAE Design-to-Test Tools From Alliance ATE

SANTA CLARA, CA, Nov. 05, 2019 (GLOBE NEWSWIRE) -- via NEWMEDIAWIRE -- Alliance ATE Consulting Group, Inc. announces today that Compound Photonics U.S. Corporation, a global leader and innovator of ...